Implementation of Fast Fourier Transform Accelerator on Coarse Grain Reconfigurable Architecture
نویسنده
چکیده
Recent technology growth permit engineer to design various complex applications on single-on-chip (SoC) related to communication, Image Processing, video processing, digital signal processing. In all of these complex algorithms, FFT blocks are one of the most computation concentrated. Here we first introduce a novel Coarse-Grain Reconfigurable Array (CGRA) which is used as a hardware accelerator to optimize the performance of system. The architecture consist of processing elements (PEs), configuration controller and interconnection network on a single chip. Subsequently we present a mapping of different length of Fast Fourier Transform (FFT) algorithms on them. In this paper, we have considered radix-(2, 4) FFT accelerators which are mapped on 4X4 PE CGRA templates. We estimated their power and energy consumption. A Field Programmable Gate Array (FPGA) is used to implement prototype of CGRA. Based on the measurements, we have compared results with other
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تاریخ انتشار 2016